The present invention relates to a method and/or architecture for implementing programmable logic devices (PLDs) generally and, more particularly, to a method and/or architecture for implementing a parallel configuration method and/or architecture for complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs).
A programmable logic device (PLD) provides an economical and efficient means for implementing predetermined Boolean logic functions in an integrated circuit. Such a device consists of, generally, an AND plane configured to generate predetermined product terms in response to a plurality of inputs, a group of fixed/programmable OR gates configured to generate a plurality of sum-of-product(SOP) terms in response to the product terms, and a number of logic elements (i.e., macrocells) configured to generate a desired output in response to the sum-of-products terms. The sum-of-products terms can also be generated using programmable NOR-NOR logic.
The arrangement and operation of components within the PLD are programmed by architecture configuration bits. The architecture configuration bits are set prior to normal operation of the PLD. The bits are set using an operation called xe2x80x9cprogrammingxe2x80x9d or xe2x80x9cconfigurationxe2x80x9d. The configuration bits can be stored in volatile memory (i.e., SRAM) or non-volatile memory (i.e., EEPROM/flash). When the configuration bits are stored in volatile memory, the configuration bits need to be loaded from a non-volatile memory, a micro controller, or some other source.
Static Random Access Memory (SRAM) based CPLDs store configuration bits in particular SRAM cells. The configuration information is stored on a separate non-volatile memory. At the time of configuration, the configuration bits are loaded from the non-volatile memory into the CPLD configuration memory cells. Such a configuration process determines the time required to program the CPLD, since the configuration process must be implemented every time the CPLD is either turned on or configured.
Referring to FIG. 1, an example of a system 10 is shown implementing a conventional configuration approach. The system 10 comprises a memory 12, a logic circuit 14 and a CPLD section 16. The memory section 12 is implemented as a low cost memory, such as a flash device. The logic circuit 14 can be a configuration logic circuit that converts configuration information from the flash memory 12 into configuration signals presented to the CPLD section 16. The logic circuit 14 communicates with the memory 12 via a bidirectional data bus 18, an address bus 20 and a control bus 22. The logic 14 presents configuration signals to the CPLD configuration section 16 via a bus 24. The CPLD configuration section 16 is shown implemented as a number of CPLD configuration blocks 30a-30n, where n is an integer.
Conventional approaches serially configure all of the blocks 30a-30n of a CPLD. A first one of the CPLD blocks 30a receives the configuration signal from the bus 24. After the CPLD block 30a is configured, configuration of the CPLD block 30b is started. The configuration continues in such a serial fashion until all of the CPLD blocks 30a-30n are configured. A disadvantages with such an approach is the length of time needed for configuration. As the number of CPLD configuration blocks (and bits) increases, the configuration time also grows.
The present invention concerns a programmable logic device comprising a plurality of configuration blocks that may be configured to store configuration information for configuring the programmable logic device. The configuration blocks may be simultaneously programmed.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a parallel configuration of CPLDs and FPGAs that may (i) configure a number of blocks (e.g., 8 PLD blocks) in parallel, (ii) provide configuration that may be faster (e.g., 8 times faster) than conventional configuration approaches), (iii) reduce system cost by using slower technologies (e.g., flash memory) when a portion of the configuration speed may be sacrificed, and/or (iv) be implemented without additional pads.